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For example, one C28x+CLA core can be used to track speed and position, while the other C28x+CLA core can be used to control torque and current loops. The dual C28x+CLA architecture enables intelligent partitioning between various system tasks.
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By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. This parallel processing capability can effectively double the computational performance of a real-time control system.
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The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The F2837xD microcontroller family features two CLA real-time control coprocessors. The C28x CPUs are further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations and the VCU accelerator, which reduces the time for complex math operations common in encoded applications. The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide 200 MHz of signal processing performance in each core. The integrated analog and control peripherals also let designers consolidate control architectures and eliminate multiprocessor use in high-end systems. The F2837xD supports a new dual-core C28x architecture that significantly boosts system performance.
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To accelerate application development, the DigitalPower software development kit (SDK) for C2000 MCUs and the MotorControl software development kit (SDK) for C2000™ MCUs are available. The TMS320F2837xD is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial motor drives solar inverters and digital power electrical vehicles and transportation and sensing and signal processing. The C2000 line includes the Premium performance MCUs and the Entry performance MCUs.
Q: –40☌ to 125☌ free-air (AEC Q100 qualification for automotive applications)Ĭ2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop performance in real-time control applications such as industrial motor drives solar inverters and digital power electrical vehicles and transportation motor control and sensing and signal processing. 100-pin PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP). 176-pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack (HLQFP). 337-ball New Fine Pitch Ball Grid Array (nFBGA). SIGMA CLIENT COMPUTE NEW CARDWARE ID WAIT TIME ISO
ISO 26262 certified up to ASIL B and IEC 61508 certified up to SIL 2 by TUV SUD. Documentation available to aid ISO 26262 system design up to ASIL D IEC 61508 up to SIL 0 up to Class C and UL 1998 up to Class 2. Developed for functional safety applications. Augments existing peripheral capability. Comparator filter for fast action for out of range. Eight Sigma-Delta Filter Module (SDFM) input channels, 2 parallel filters per channel. Three Enhanced Quadrature Encoder Pulse (eQEP) modules. Dead-band support (on both standard and high resolution). High resolution on both A and B channels of 8 PWM modules. 16 High-Resolution Pulse Width Modulator (HRPWM) channels. 24 Pulse Width Modulator (PWM) channels with enhanced features. Eight windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references. High, low, and zero-crossing compare, with interrupt capability. 
Hardware-integrated post-processing of ADC conversions. Single Sample-and-Hold (S/H) on each ADC. 3.5 MSPS each (up to 14-MSPS system throughput). 1.1 MSPS each (up to 4.4-MSPS system throughput). Up to four Analog-to-Digital Converters (ADCs). SIGMA CLIENT COMPUTE NEW CARDWARE ID WAIT TIME SERIAL
Four Serial Communications Interfaces (SCI/UART) (pin-bootable). Two Multichannel Buffered Serial Ports (McBSPs). Three high-speed (up to 50-MHz) SPI ports (pin-bootable). Two Controller Area Network (CAN) modules (pin-bootable). 
Support for 12-pin 3.3 V-compatible Universal Parallel Port (uPP) interface. Multiple Low-Power Mode (LPM) support with external wakeup. Expanded Peripheral Interrupt controller (ePIE). Up to 169 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins with input filtering. 
Dual 6-channel Direct Memory Access (DMA) controllers. Two External Memory Interfaces (EMIFs) with ASRAM and SDRAM support. Two internal zero-pin 10-MHz oscillators. Dual-zone security supporting third-party development. 172KB (86KW) or 204KB (102KW) of RAM (ECC-protected or parity-protected). Executes code independently of main CPU. IEEE 754 single-precision floating-point instructions. Two programmable Control Law Accelerators (CLAs). IEEE 754 single-precision Floating-Point Unit (FPU).
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